JN driving ---------- The display is composed of 128*56 dots, with alternating triangles of blue and yellow, forming a 128*23 bicolour display. Pixels are arranged as such: |-/ |/ /| /_| with the top pixel being blue, and the bottom yellow. these are tiled in a 128*56 array across the display. The display has 64 grids, which allows for 1/64th duty cycle multiplexing. Interface is via several signals: 1,2,3 - filament+ (connects to 5V through 2.7 ohm and 4.7 ohm resistors in parallel) 4 - VDD logic supply (connects to 3.3V or 5V) 5 - GND 6 - GND 7 - VDD2 plate/grid supply (connects to 57V DC through a 22 ohm resistor, and PNP transistor to enable it) 8 - BK blanking pulse (high = blank, low = display) 9 - LAT latch signal (high = latch new data from shifters to output) 10 - DEN data enable (low = drive columns B/C, high = drive columns A/D) 11 - GCP greyscale clock (pulse high 6 times during the scan to effect a greyscale PWM) 12 - SDO2 serial output data bit 2 (usually not used) 13 - SDO1 bit 1 14 - SDO0 bit 0 15 - CLK data clock (data on SDIx is clocked in on rising edges) 16 - SDI0 serial input data bit 0 17 - SDI1 bit 1 18 - SDI2 bit 2 19,20,21 - filament- (connects to ground through two parallel 12 ohm resistors) The display is typically driven with 3.3V logic and 3.3V on VDD, and 57V on VDD2. A PNP transistor or similar is usually used to control power to VDD2, and is enabled via a protection circuit. (see below) To refresh the display, data is loaded into SDI0-2 using CLK, then after 112+64 bits are loaded, BK is pulled high, LAT is pulsed high, and BK is pulled low. The output drivers will latch the current shifter contents at this time. A complete "frame" takes a total of 64 "scans". The pixels on the display are arranged in columns: ABCDABCDABCD ............ row 0 ............ row 1 ............ row 2 ............ row n There are four column "groups" as denoted above, labelled A, B, C, D. All the pixels of every "A" column in row 0 are connected together, every "B" pixel in row 0 are connected together, and so forth. Pixels in rows 1, 2, 3, 4, etc. are separately connected in the same way. Since the display has 56 rows, this means there are 56*4 = 224 separate outputs that drive the dots directly. This sounds like a lot of signals in such a small space and it is, but looking at the back side of the display all this routing can be seen. The display is multiplexed by way of the 64 grids that cover the columns of pixels, and only allows one set to be lit at any one time. Unlike a conventional VFD, where a single grid is enabled at a time, on these displays TWO grids are enabled at once. This is done to prevent ghosting of nearby columns which would otherwise happen. Likewise, out of the four columns in the set, only two are ever lit at a time, again to prevent ghosting. 1 2 3 4 5 6 7 8 9 64 /\/\/\/\/\/\/\/\/\ /\/\/\ ABCDABCDABCDABCDAB...CDABCD Each grid covers 2 columns. As can be seen, AB and CD are pairs of columns covered by the grids. Because there's 128 columns, and 64 grids, each grid must cover 2 columns. The grids are enabled in this pattern: 64,1 scan 0 1,2 scan 1 2,3 scan 2 3,4 scan 3 4,5 scan 4 5,6 scan 5 7,8 scan 6 ... 63,64 scan 63 This means the first scan, grids 1 and 64 are both on while 2-63 are off; on the second scan grids 1/2 are on while 3-64 are off and so on. The first scan has this "overlap" where the first/last grids are on, while the rest have two adjacent grids on. Starting on scan 1 for simplicity, the following occurs: scan 1: / \ ABCDABCDABCDABCDAB scan 2: / \ ABCDABCDABCDABCDAB scan 3: / \ ABCDABCDABCDABCDAB On scan 1, columns 0-3 are enabled by the two grids being on On scan 2, columns 2-5 are enabled by the two grids On scan 3, columns 4-7 are enabled The goal of this is to only illuminate the two INNER columns of each set of four, while the two outer columns of the 4 are blanked. This prevents bleed because the following happens: / \ ABCDABCDABCDABCDAB X..XX..XX..XX..XX. Any particular enabled column is in the very center of the two enabled grids, D and A in this case, while BC are blanked. B/C are on the edge of the grids, so i.e. column 6 (B) has an enabled grid over the top of it, while column 7 (C) has a disabled grid over the top of it. This prevents bleeding/ghosting, because the abutting columns to enabled grids are always going to be blanked. On the next scan, the roles reverse and B/C will be illuminated while A/D are blanked. / \ ABCDABCDABCDABCDAB ..X..XX..XX..XX..X So basically the display is scanned left to right, in sets of 4 columns, with 2 blanked and 2 visible. 64 scans make up a frame. To properly scan the display, the following column data is sent out: scan 0: AD column 0,127 grid 64,1 (because of the "wraparound" effect) scan 1: BC column 1,2 grid 1,2 scan 2: AD column 4,3 grid 2,3 ("backwards" because the column order where D/A meet: abcDAbcd) scan 3: BC column 5,6 grid 3,4 scan 4: AD column 8,7 grid 4,5 scan 5: BC column 9,10 grid 5,6 ... scan 63: BC column 125,126 grid 63,64 scan 0: AD column 0,127 grid 64,1 The data is sent to the glass in the following order: ("AD" scan, DEN high) . = this pixel is not used and is blanked. each number is the clock #. i.e. 0 = first bit shifted in, 1 = second bit shifted in, etc. ABCD 0..1 (blue) row 0 2..3 (yellow) row 1 4..5 (blue) row 2 ... 110..111 (yellow) row 55 ("BC" scan, DEN low) ABCD .01. (blue) row 0 .23. (yellow) row 1 .45. (blue) row 2 ... .110111. (yellow) row 55 It takes exactly 112 clocks to shift all the pixels in for 2 columns. 2*56 = 112. Data is entered as it is shown in the two diagrams above. After the 112 data bits for the pixels are entered, 64 more are entered for the grids. Grids are numbered 1-64 in order after the data bits, and are written as indicated above. DEN ===================================x==== BK ________________________________------__ LAT _________________________________-______ CLK ____-_-_-_-_-_-_-_-_-_-_-_-_-_-_________ SDIx ------------- Data is clocked into the shift register on the rising edge of CLK. Data on SDIx should be set up 100ns or more before CLK rises. Minimum period is most likely 100ns for high and low periods, giving a maximum clock rate of 5MHz (200ns period). I am clocking it at half this, though. The first 112 bits clocked in will be the 112 bits of grid data. The three data lines determine the brightness for a particular pixel. 0 = off, 7 = on 100%, 1 = 1/7th, 2 = 2/7th, etc. duty cycle. The last 64 bits clocked in will the 64 bits of grid data. For "on" grids, ALL THREE bits must be set (i.e. 7). For "off" grids, all three bits must be clear (i.e. 0). Otherwise weird stuff could happen since the grids would PWM too. Don't do this. At this point you can wait awhile (if you scanned your data in fast) before hitting BK and latching the new data. I am using a 70Hz refresh rate for now which means there are 70*64 = 4480 "scans" per second. BK should be high for 10uS minimum for inter-scan blanking. LAT should be pulsed about 1uS after the start of blanking. The LAT pulse should be 500ns or longer. This will latch the previously shifted in data to the output drivers. DEN is updated right after the LAT pulse. It is high for AD data and low for BC data. This signal is the select for a 1:2 demultiplexer that drives the A/D or B/C outputs, basically. It will drive one set and blank the other. It must only be changed in blank to prevent ghosting. DEN does not affect the grids. This completes one "scan". The last part to deal with is duty cycle. This is done using the GCP input. Basically the way it works, is each time it is pulsed, the drivers are enabled or disabled depending on the 3 bit brightness code: input code vs. pixel output (- = on, _ = off) 0 ______________________________________________________________________ 1 ______________________________________________________________-----___ 2 ____________________________________________________---------------___ 3 ___________________________________________------------------------___ 4 ______________________________-------------------------------------___ 5 ____________________-----------------------------------------------___ 6 _____________------------------------------------------------------___ 7 _____--------------------------------------------------------------___ GCP _____________-______-__________-___________-________-_________-_______ BK -----______________________________________________________________--- The BK pulse resets the GCP counter, and each pulse of GCP will "Step" the PWM. This means input code 1 will only light up the pixel after 6 pulses of GCP. An input code of 2 will light the pixel up after 5 pulses, and so on. An input code of 6 will light up the pixel after the first GCP pulse. Input code 7 always lights it up, and a code of 0 never lights it up. GCP is thus pulsed 6 times during a complete "scan" to do all 8 levels of brightness. These pulses should occur on a curve, with them getting closer together as blank is approached in a log fashion or similar to approximate the brightness curve of the human eye. The last thing to discuss is protection circuitry. There should be a monostable (74HC123) that is connected to CLK and SDI0 that detects if scanning stops. If scanning stops, the display will rapidly be destroyed because 2 columns of pixels will get 64x their rated duty cycle, and thus experience rapid phosphor degredation to say the least. I use a '123 with /A connected to CLK and B connected to SDI0. A 56K R and .01uF C is used for the timing. One of the outputs disables the SMPS that generates the voltage, and the other drives an NPN transistor which drives the PNP transistor that cuts power to VDD2 of the display glass itself to instantly kill the HV in the event of a scan/software failure. The Q output of the '123 goes high when normal scan is occuring, and the /Q output goes low. I ran the Q output to the NPN/PNP combo, and /Q to my SMPS' active low enable.