Ampex model 1600 core memory board.

16K*18 bits (board is capable of 16K*20 bits, or 32K*10 bits maximum).
Board has several points that can be jumpered to set it up for 10 or 20 bit 
word sizes.

This board has been jumpered for 18 bits wide (Well, 20 but 2 bits are 
disabled and the corresponding chips and core planes are missing).


Pins:

/RST - this reset input should be held low during powerup and power down.

A0-A14 - address of the word you wish to read.  On this module, A14 is not used- it's only used on the 8, 9, or 10 bit wide models.

R/W - determines if this is a read or write operation. High = read, low = write.

D0-D17 in - data to be written is input on these pins.

D0-D17 out - data in the data latch is output on these pins.  NOTE: these pins are open collector output, and must be pulled up with 4.7K resistors or similar.  They will only output data when /CE0 is low and CE1 is high.

/odd write enable - when low, allows odd data bits to be written.
/even write enable - when low, allows even data bits to be written.

rewrite - when high, allows data to be rewritten, otherwise the location is kept all 0's instead.

EN0a, EN0b - XOR inputs that act as more chip enables.  There's three pairs of
these inputs;  both inputs of the pair must be i.e. high or low before the
board will work.  This allows paralleling 8 identical boards by feeding a
3 bit match address into EN0a, EN1a, and EN2a then using EN0b, EN1b, EN2b as
3 extra address lines.

/CE0 - must be low to start a read/write cycle

CE1 - must be high to start a read/write cycle


To read a word of memory, the following things are done:

1. /RST should be high

2. apply the address on A0-A13 (or A14)

3. R/W should be high

4. EN0,1,2 pairs must have the same logic state

5. /CE0 goes low

6. CE1 goes high

7. after a read occurs, Read Done is pulsed to indicate it finished

8. data is available on D0-D17 out until CE1 goes low again.


To write memory works similar, only R/W is held low instead and D0-D17 in
are loaded with the word to write.

The even/odd write enables determine which half (or both halves) of the word
will be written.  even write enable allows D0,D2,D4, etc to be written, while
odd write enable allows D1,D3,D5, etch to be written.

This way, the CPU can only update half of the word if needed.  If this function
is not required, both enables can simply be grounded to always write full
words.


The only part I am unsure about is the rewrite input. 


P1:

A(bottom)


 1 - +15V
 2 - +15V
 3 - GND
 4 - GND
 5 - +5V
 6 - +5V
 7 - nc
 8 - D1 in
 9 - D0 in
10 - D3 in
11 - D2 in
12 - A7
13 - A6
14 - GND
15 - GND
16 - GND
17 - GND
18 - GND
19 - GND
20 - GND
21 - GND
22 - GND
23 - GND
24 - GND
25 - GND
26 - GND
27 - GND
28 - GND
29 - GND
30 - GND
31 - GND
32 - GND
33 - GND
34 - GND
35 - GND
36 - GND
37 - GND
38 - GND
39 - GND
40 - GND
41 - GND
42 - GND
43 - D7 in
44 - D6 in
45 - D9 in
46 - D8 in
47 - Dxx in (route cut)
48 - Dxx in (route cut)
49 - GND
50 - GND


B(top)


 1 - +15V
 2 - +15V
 3 - GND
 4 - GND
 5 - +5V
 6 - +5V
 7 - nc
 8 - A5
 9 - A4
10 - A3
11 - A2
12 - A1
13 - A0
14 - GND
15 - GND
16 - D1 out
17 - D0 out
18 - D3 out
19 - D2 out
20 - D5 out
21 - D4 out
22 - GND
23 - GND
24 - GND
25 - CE1
26 - D5 in
27 - D4 in
28 - /CE0
29 - EN2a
30 - EN2b
31 - nc (route cut)
32 - GND
33 - GND
34 - EN1a
35 - EN1b
36 - /RST
37 - EN0a
38 - EN0b
39 - R/W
40 - GND
41 - GND
42 - GND
43 - D7 out
44 - D6 out
45 - Read Done (active high, pulses load when read is done)
46 - CE Low (pulses high when CE goes low, ending read)
47 - Cycle Done (pulses high when read/write cycle is done)
48 - Data Latched (pulses high when data is latched into register)
49 - GND
50 - GND



P2:

A(bottom)

 1 - GND
 2 - GND
 3 - GND
 4 - GND
 5 - GND
 6 - GND
 7 - GND
 8 - GND
 9 - GND
10 - GND
11 - GND
12 - GND
13 - GND
14 - GND
15 - GND
16 - GND
17 - GND
18 - GND
19 - GND
20 - GND
21 - pulled up to 5V via 1K
22 - GND
23 - rewrite?
24 - A14     (not used on this model)
25 - A12
26 - A11
27 - D17 in
28 - D16 in
29 - nc      (would be -5V on other models)
30 - nc
31 - +15V
32 - +15V
33 - GND
34 - GND
35 - +5V
36 - +5V

B(top)

 1 - D9 out
 2 - D8 out
 3 - Dxx out (route cut)
 4 - Dxx out (route cut)
 5 - D11 out
 6 - D10 out
 7 - GND
 8 - D11 in
 9 - D10 in
10 - D13 in
11 - D12 in
12 - D15 in
13 - D14 in
14 - GND
15 - GND
16 - D13 out
17 - D12 out
18 - D15 out
19 - D14 out
20 - D17 out
21 - D16 out
22 - GND
23 - /odd write enable
24 - /even write enable
25 - A10
26 - A9
27 - A13
28 - A8
29 - GND
30 - nc
31 - +15V
32 - +15V
33 - GND
34 - GND
35 - +5V
36 - +5V