:!7Intel PLD Library - V1.3XR10717&5C031-CMOS And-Or Gate Array with Output Macrocells ALT_20_LO4ALT_EP300_ARRAY 00C D Dd0Tt Dp`L@(  D @` $ H l D$Hl @`10718&5C032-CMOS And-Or Gate Array with Output Macrocells ALT_320_LOALT_EP320_ARRAY 00C 10719&5C060-CMOS And-Or Gate Array with Output MacrocellsALT_24ALT_EP600_ARRAY 00C 10720&5C090-CMOS And-Or Gate Array with Output MacrocellsALT_9000ALT_EP900_ARRAY 00C (,C  C 10721&5C121-CMOS And-Or Gate Array with Output Macrocells ALT_12_LOALT_EP1200_ARRAY 00C (21152&5C180-CMOS And-Or Gate Array with Output Macrocells DIRECT_68 DIR_EP1800_ARRAY 11C D31152&5C180568 Pin PLCC To 40 Pin DIP OPTPLC-180 Adaptor Required DIRECT_68_OPT OPT_EP1800_ARRAY 11C (11152&5C180*68 Pin PLCC To 40 Pin DIP Adaptor RequiredALT_68 ALT_EP1800_ARRAY 00C (12401&5AC312High Performance EPLD INTEL_3120 5AC312_ARRAY 00C 5  5 12692&5AC324High Performance EPLD INTEL_324 5AC324_ARRAY 00C (,13331&85C060,CHMOS And-Or Gate Array w/ Output MacrocellsINT_24ALT_EP600_ARRAY 00C 14252&iPLD610,CHMOS And-Or Gate Array w/ Output MacrocellsINT_24ALT_EP600_ARRAY 00C 13332&85C090,CHMOS And-Or Gate Array w/ Output MacrocellsINT_9000ALT_EP900_ARRAY 00C (,C  C 14253&iPLD910,CHMOS And-Or Gate Array w/ Output MacrocellsINT_9000ALT_EP900_ARRAY 00C (,C  C 13213&85C220High Performance uPLD INTEL_320_LOALT_EP320_ARRAY 00C 13334&85C224High Performance uPLD INTEL_224@ INT_224_ARRAY 00C 12689&85C508)CHMOS High Performance Decoder/Latch uPLD INTEL_508 85C805_ARRAY 00C 13212&85C96080960 K-SERIES Bus Control uPLD INTEL_960 85C960_ARRAY 00C 13811&85C22V10-CMOS And-Or Gate Array with Output Macrocells INT85C22V10INT85C22V10_ARRAY 00C h,XlX Dp@$ ht|\PL$ $ dtH4( h`(P  x@$P|,Xlv hX4`XXX14116& iPLD22V10Subset of 85C22v10 iPLD22V10iPLD22V10_ARRAY 00C `,XlX Dp@$ `lt|\PL$ $ dtH4 ``(P  x@$P|,Xl `X4`X14730&FX740_44High Density CMOS FPGAFX740_44_PIN_FMY@FX740_44_PIN_ARRAY 11C ,24730&FX740_68High Density CMOS FPGAFX740_68_PIN_FMY@FX740_68_PIN_ARRAY 11C D14468&FX780_84High Density CMOS FPGAFX780_84_PIN_FMY@FX780_84_PIN_ARRAY 11D T24468& FX780_132)High Density CMOS FPGA (Adaptor Required)FX780_132_PIN_FMY@FX780_132_PIN_ARRAY 11D  DIRECT_68_OPTALTERAASAP_180  X   (""!     "P"!     " ALT_20_HIINTELASAP_300  X   2  X ALT_20_LOINTELASAP_300~ ~ X   2  X~ #X ALT_320_LOINTELASAP_320  X   2  X ALT_24INTELASAP_600  X   2  X   ALT_900INTELASAP_900  X   2(()*  !"#$%&'()+X+()+  !#$'( ALT_12_HIINTELASAP_120: : X   (('&  !"#$%&X:'!"#$%&'( ALT_12_LOINTELASAP_120  X   (('&  !"#$%&X'!"#$%&'(ALT_68INTELASAP_180  X  } (('  !"#$%&'(P(!  !"#$%&( INTEL_312INTELINT312    2 2Z     Z+,- INTEL_324INTELINT324&  X  2 2d( ! !&  "#$%&'( ! Z$ INTEL_320_LOINTELASAP_320  X   2  X  INTEL_224INTELINT_224           INTEL_508INTELINT_508  X  2 2  #XINT_24INTELASAP_600  X D  2  X   INT_900INTELASAP_900  X D  2(()*  !"#$%&'()+X+()+  !#$'( DIRECT_68INTELASAP_180  X  } D4"DCBA <;:9876210/.-,4P4##"DCBA <;:9876210/.-,4 INTEL_960INTEL85C960  X  2 2  #X$ INT85C22V10INTEL85C22V10  X & 2       iPLD22V10INTEL85C22V10  X & 2      FX740_44_PIN_FMYINTELFX740      2, "#$% " "$%+w,-wFX740_68_PIN_FMYINTELFX740      2D#34#"67D#34 "#3467D+w,-wFX780_84_PIN_FMYINTELFX780      2TD# &.;AGPF  !"#$%'()*+,-/01236789:<=>?@BCEFHIJKLMNOQRSTDD &.;AGPD+,-FX780_132_PIN_FMYINTELFX780      2# +,-OPT_EP1800_ARRAYQuad A, Macrocell 1-12@)    xX#       !#Quad B, Macrocell 13-24@)@)    xXQuad C, Macrocell 25-36R@)    xXQuad D, Macrocell 37-48{@)    xXMacrocell 1-12 I/O Arch<    Macrocell 13-24 I/O Arch<<    $%&Macrocell 25-36 I/O Archx<    $%&Macrocell 37-48 I/O Arch<    $%&Macrocell 1-12 OE/CLK    $%&Macrocell 13-24 I/O Arch    $%&Macrocell 25-36 I/O Arch    $%&Macrocell 37-48 I/O Arch    $%& TURBO Bits    $%&ALT_EP300_ARRAYAnd-Or     $   ! # Output Enable       $ Sync Preset/Async Reset  H     $ +~Output / Feedbackh 8     ALT_EP310_ARRAYAnd-Or     $   ! # Output Enable       $ Sync Preset/Async Reset  H     $ +~Output / Feedbackh 8     .ALT_EP320_ARRAYAnd-Or      $   ! # Reference       $ Architecture Control@        TURBO/MISER`      ALT_EP600_ARRAYMacrocell 1-8 And      (     ! #Macrocell 9-16 And       ( Macrocell 1-8 I/O Arch (     (Macrocell 9-16 I/O Arch ((     ( TURBO bit #1P     + TURBO bit #2Q     +ALT_EP900_ARRAYMacrocell 1-12!     x !H #$'  !#$'! #Macrocell 13-24!!     x !H #$'Macrocell 1-12 I/O ArchC<      ! #$'Macrocell 13-24 I/O ArchC<      ! #$' TURBO bit #1 C      ! #$'+ TURBO bit #2 C      ! #$'+ALT_EP1200_ARRAYMacrocells A1, A2 & A3    v %$#@ "!(& %$#"!!#Macrocells B1, B2 & B3    v %$#@ "!Macrocell 1-14 I/O Arch;     %$# "!Macrocell 15-28 I/O Arch;     %$# "! Clock Mode&;     %$# "! TURBO bit);     %$# "!+Power on reset bit*;     %$# "!+ALT_EP1800_ARRAYQuad A, Macrocell 1-12@)    xX   "!$ # &%!# Quad B, Macrocell 13-24@)@)    xXQuad C, Macrocell 25-36R@)    xXQuad D, Macrocell 37-48{@)    xXMacrocell 1-12 I/O Arch<    Macrocell 13-24 I/O Arch<<    Macrocell 25-36 I/O Archx<    Macrocell 37-48 I/O Arch<    Macrocell 1-12 OE/CLK    Macrocell 13-24 I/O Arch    Macrocell 25-36 I/O Arch    Macrocell 37-48 I/O Arch     TURBO Bits     5AC312_ARRAYAnd3    @  !"#$%&'()*+,-./D ! # Input Register Asynch. Clk PTs3     DMacrocell Architecture Bits 5`   0 Input Control Bits5      Turbo Bit5    5AC324_ARRAYPTERMSZ    @@ABCDEFGPQRSTUVWx !'"$#  "$$  "$PTERMSZZ    @@ABCDEFGPQRSTUVWxInput Latch/Clock PTerms    px+0 I/O Arch Bits    ` Input Arch Bitsp   p*  INT_224_ARRAYAnd-Or`     ,     !#Architecture Control`        MISER/TURBO        85C805_ARRAYPTERMS    @   ! "#DIR_EP1800_ARRAYQuad A, Macrocell 1-12@)    DCBAxX 26789: ,-./1;<0!DCBA#Quad B, Macrocell 13-24@)@)    DCBAxXQuad C, Macrocell 25-36R@)    DCBAxXQuad D, Macrocell 37-48{@)    DCBAxXMacrocell 1-12 I/O Arch<    DCBAMacrocell 13-24 I/O Arch<<    Macrocell 25-36 I/O Archx<    Macrocell 37-48 I/O Arch<    Macrocell 1-12 OE/CLK    Macrocell 13-24 I/O Arch    Macrocell 25-36 I/O Arch    Macrocell 37-48 I/O Arch     TURBO Bits     85C960_ARRAYPTERMS    @    ! "#INT85C22V10_ARRAYAnd-Or:       ,X+*)('&%$ #" !   ! " # (?? Output Enable0@    ,X+*)('&%$ #" ! Architecture (S0 & S1)@X    ,Architecture (S2)@l    , Architecture (C0)@v    ,A. Reset/S. Preset @X    ,X+*)('&%$ #" ! +iPLD22V10_ARRAYAnd-Or:       ,X+*)('&%$ #" !   ! " # (?? Output Enable0@    ,X+*)('&%$ #" ! Architecture (S0 & S1)@X    ,A. Reset/S. Preset @lX    ,X+*)('&%$ #" ! +FX740_44_PIN_ARRAYFUSESp>   M0+,!  !&'()*FX740_68_PIN_ARRAYFUSESp>   M0! BC!2 $%&'()*+,-./01289:;<=>?@AFX780_84_PIN_ARRAYFUSES|   H 54FX780_132_PIN_ARRAYFUSES|   H