›/ Bū7Cypress Semiconductor PLD Library - V2.30C10354& PALCE16V8#Based CMOS Programmable Array Logic CE16V8_FMYAĀ CE16V8_ARRAY 00C 10454&PAL16L8AAnd-Or-Invert Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 14898& PAL16L8-4And-Or-Invert Gate ArrayCYP_20_4CYP_20_4_PIN_INVERT_ARRAY 00C 14132& PAL16L8-5And-Or-Invert Gate ArrayCYP_20_5CYP_20_5_PIN_INVERT_ARRAY 00C 11093&PALC16L8CMOS And-Or-Invert Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 10455&PAL16R8ARegistered And-Or Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 14901& PAL16R8-4And-Or-Invert Gate ArrayCYP_20_4€CYP_20_4_PIN_INVERT_ARRAY 00C 14133& PAL16R8-5And-Or-Invert Gate ArrayCYP_20_5€CYP_20_5_PIN_INVERT_ARRAY 00C 11099&PALC16R8!CMOS Registered And-Or Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 10456&PAL16R6ARegistered And-Or Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 14900& PAL16R6-4And-Or-Invert Gate ArrayCYP_20_4€CYP_20_4_PIN_INVERT_ARRAY 00C 14134& PAL16R6-5And-Or-Invert Gate ArrayCYP_20_5€CYP_20_5_PIN_INVERT_ARRAY 00C 11097&PALC16R6!CMOS Registered And-Or Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 10457&PAL16R4ARegistered And-Or Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 14899& PAL16R4-4And-Or-Invert Gate ArrayCYP_20_4€CYP_20_4_PIN_INVERT_ARRAY 00C 14135& PAL16R4-5And-Or-Invert Gate ArrayCYP_20_5€CYP_20_5_PIN_INVERT_ARRAY 00C 11095&PALC16R4!CMOS Registered And-Or Gate ArrayCYP_20CYP_20_PIN_INVERT_ARRAY 00C 12765&CY10E301*ECL And-Or Gate Array with Output PolarityCY100E301_FAMILYCY100E301_ARRAY 00C 12763& CY100E301*ECL And-Or Gate Array with Output PolarityCY100E301_FAMILYCY100E301_ARRAY 00C 12769&CY10E302*ECL And-Or Gate Array with Output PolarityCY100E301_FAMILYCY100E302_ARRAY 00C 12767& CY100E302*ECL And-Or Gate Array with Output PolarityCY100E301_FAMILYCY100E302_ARRAY 00C 13281&PLDC18G8-CMOS And-Or Gate Array with Output MacrocellsCYP18G80CYP_PAL18G8_ARRAY 00C D$DhˆŦĖđ4Tx˜ŧÜ D Ü˙˙˙ā¸˙˙˙Ā”˙˙˙ p˙˙˙€L˙˙˙`(˙˙˙@˙˙˙ āū˙˙ D @`€ Āā $ H l  ´ Ø ü D$Hl´Øü ÷˙˙ ø˙˙@ų˙˙`ú˙˙€û˙˙ ü˙˙Āũ˙˙āū˙˙12752& PLDC20RA10-CMOS And-Or Gate Array with Output Macrocells CYP_20RA10ĐCYP_PAL20RA10_ARRAY 00C 10452& PALC22V10-CMOS And-Or Gate Array with Output Macrocells CYP_C22V10°CYP_PAL22V10_ARRAY 00C `,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙13411& PALC22V10B-CMOS And-Or Gate Array with Output Macrocells CYP_C22V10BđCYP_PAL22V10_ARRAY 00C 'Requires new PLCC module/PN# 03-05882-5`,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙13341& PAL22V10C-CMOS And-Or Gate Array with Output Macrocells CYPAL22V10C0CYP_PAL22V10C_ARRAY 11D  Adaptor required (DIP pkg. only)`,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙13339& PAL22VP10C-CMOS And-Or Gate Array with Output Macrocells CYP_22VP10C0CYP_PAL22VP10C_ARRAY 11D  Adaptor required (DIP pkg. only)d,X¸äœČØl˜X „ DpØ@ø$„°ÄÎ dvt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙¨˙˙˙ d`(P  xˆ@ Ėø$P|¨Ô,XlvĸÎ dX„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙XXŠé˙˙â˙˙˙25229& PALCE22V10-CMOS And-Or Gate Array with Output Macrocells CYP_C22V10D CYP_PALC22V10D_ARRAY 00C `,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙14131& PALC22V10D-CMOS And-Or Gate Array with Output Macrocells CYP_C22V10D CYP_PALC22V10D_ARRAY 00C `,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙10453& PLDC20G10-CMOS And-Or Gate Array with Output MacrocellsCYP_C_24°CYP_PAL20G10_ARRAY 00C T,Œ¸D¤Đ0\ŧčH t Ô ` Œ ė x TĀ Ô˙˙˙` ¨˙˙˙ |˙˙˙  P˙˙˙@$˙˙˙āøū˙˙€Ėū˙˙  ū˙˙Ātū˙˙`Hū˙˙ T`Ā €ā@  ` Ā ė DpœČô Lx T,X„°Ü4`Œ¸@ō˙˙ ķ˙˙õ˙˙`ö˙˙Ā÷˙˙ ų˙˙€ú˙˙āû˙˙@ũ˙˙ ū˙˙13280& PLDC20G10B-CMOS And-Or Gate Array with Output Macrocells CYP_20G10B°CYP_PAL20G10_ARRAY 00C T,Œ¸D¤Đ0\ŧčH t Ô ` Œ ė x TĀ Ô˙˙˙` ¨˙˙˙ |˙˙˙  P˙˙˙@$˙˙˙āøū˙˙€Ėū˙˙  ū˙˙Ātū˙˙`Hū˙˙ T`Ā €ā@  ` Ā ė DpœČô Lx T,X„°Ü4`Œ¸@ō˙˙ ķ˙˙õ˙˙`ö˙˙Ā÷˙˙ ų˙˙€ú˙˙āû˙˙@ũ˙˙ ū˙˙13952& PLD20G10C-CMOS And-Or Gate Array with Output Macrocells CYPAL22V10C0CYP_PAL22V10C_ARRAY 00C `,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙10458&PALC20R8 20R8 - Subset of 22V10 and 20G10CYP_C_24CYP_PAL20R8_ARRAY 00C subset of 20G10subset of 22V1010459&PALC20R6 20R6 - Subset of 22V10 and 20G10CYP_C_24°CYP_PAL20R6_ARRAY 00C subset of 20G10subset of 22V10(Āč ° Ø˙˙˙°˙˙˙ ˜° Ø (PPö˙˙čū˙˙10460&PALC20R4 20R4 - Subset of 22V10 and 20G10CYP_C_24°CYP_PAL20R4_ARRAY 00C subset of 20G10subset of 22V10$(@h€¨Āč $` Ø˙˙˙H°˙˙˙0ˆ˙˙˙`˙˙˙ $0H` ˆ ° Ø $(Px  ö˙˙¸÷˙˙Đũ˙˙čū˙˙10461&PALC20L8 20L8 - Subset of 22V10 and 20G10CYP_C_24 CYP_PAL20L8_ARRAY 00C subset of 20G10subset of 22V10D(@h€¨Āč(@h€¨Āč DĀØ˙˙˙¨°˙˙˙ˆ˙˙˙x`˙˙˙`8˙˙˙H˙˙˙0čū˙˙Āū˙˙ D0H`x¨Āč 8 ` ˆ ° Ø D(Px Čđ@@÷˙˙Xø˙˙pų˙˙ˆú˙˙ û˙˙¸ü˙˙Đũ˙˙čū˙˙10462& PALC20L10!20L10 - Subset of 22V10 and 20G10CYP_C_24 CYP_PAL20L10_ARRAY 00C subset of 20G10subset of 22V10T( Č@h‍ HĀč`ˆ( Č@ T°Ø˙˙˙8°˙˙˙Āˆ˙˙˙H`˙˙˙Đ8˙˙˙X˙˙˙āčū˙˙hĀū˙˙đ˜ū˙˙xpū˙˙ TxđhāXĐHĀ8°Ø(Px Čđ@ T(Px Čđ@hPû˙˙Čû˙˙@ü˙˙¸ü˙˙0ũ˙˙¨ũ˙˙ ū˙˙˜ū˙˙˙˙˙ˆ˙˙˙10463&PALC20L2 20L2 - Subset of 22V10 and 20G10CYP_C_24CYP_PAL20L2_ARRAY 00C subset of 20G10subset of 22V1010464&PALC18L4 18L4 - Subset of 22V10 and 20G10CYP_C_24CYP_PAL18L4_ARRAY 00C subset of 20G10subset of 22V1010465&PALC16L6 16L6 - Subset of 22V10 and 20G10CYP_C_24CYP_PAL16L6_ARRAY 00C subset of 20G10subset of 22V1010466&PALC14L8 14L8 - Subset of 22V10 and 20G10CYP_C_24CYP_PAL14L8_ARRAY 00C subset of 20G10subset of 22V1010467& PALC12L10!12L10 - Subset of 22V10 and 20G10CYP_C_24CYP_PAL12L10_ARRAY 00C subset of 20G10subset of 22V1013945&PLD610CMOS PLD CY7B326CYP610 610_ARRAY 00C 13946&CY7B333BCMOS PLD CY7B333BCY7B333B_FAMILYCY7B333B_ARRAY 00C 13757&CY7B336€+CMOS Programmable Synchronous State Machine CYP_7B337 CY7B336_ARRAY 00C 13758&CY7B337+CMOS Programmable Synchronous State Machine CYP_7B337 CY7B337_ARRAY 00C 13759&CY7B338€+CMOS Programmable Synchronous State Machine CYP_7B337 CY7B336_ARRAY 00C 13760&CY7B339+CMOS Programmable Synchronous State Machine CYP_7B337 CY7B337_ARRAY 00C 12262&CY7C330+CMOS Programmable Synchronous State MachineCY7C330ā CY7C330_ARRAY 00C ēB  ēB 12263&CY7C331!CMOS Asynchronous Registered EPLDCY7C330ā CY7C331_ARRAY 00C ž.  ž. 12264&CY7C332!CMOS Registered Combinatorial PLDCY7C332@ CY7C332_ARRAY 00C 14130&CY7C335 CMOS Synchronous Registered EPLDCY7C335ā CY7C335_ARRAY 00C ôD  ôD 13275&CY7C342@ CMOS EPLD MAX (Adaptor Required) MAX_FMY_342 342_ARRAY 00C (13276&CY7C343@ CMOS EPLD MAX (Adaptor Required) MAX_FMY_343 343_ARRAY 00C (13277&CY7C344@ CMOS EPLD MAX (Adaptor Required) MAX_FMY_344 344_ARRAY 00C 13326&CY7C361@*CMOS High Speed Programmable State Machine CYP_7C361_FMY CY7C361_ARRAY 00C 14770&CY7C371@!CMOS High Speed Programmable CPLD CYP_7C371_FMY CY7C371_ARRAY 00C , CYP_C22V10CYPRESSCYPRESSV ôF F ô ô –     ôFPÃ*   +Ņ,Č-Ņ CYP_C22V10BCYPRESSCYPRESSB ĖÉ É Ė Ė d    ĖÉPÃ* +Y,–-Y  +Ņ,Č-ŅCYP_C_24CYPRESSCYPRESSV ôF F ô ô –     ôFPÃ*   +Ņ,Č-Ņ CYP_20G10BCYPRESSCYPRESSV ôâ â ô ô –     ôâPÃ*   +Ņ,Č-Ņ CYP_20RA10CYPRESSCY20RA10 ęâ â ô ô –     ôâPÃ* +Â,-  +Ņ,Č-Ņ CYPAL22V10CCYPRESSCP22V10C ôļ ļ ô ô      ôļ   CYP_22VP10CCYPRESSC22VP10C ôļ ļ ô ô      ôļ  CYP_20CYPRESSCYPRESSV ôF F ô ô –  d   ôFô*   +Ņ,ú-ŅCYP_20_5CYPRESSCYP20-5ôļ ļ ô ô  d   ôļô*   +Ņ,ú-ŅCY7C330CYPRESSCY7C33Xôâ â ô ô –   ôâPÃ+Ö+Ņ,Č-ŅCY7C335CYPRESSCY7C335ôâ â ô ô –    ôâPÃ+Ö+Ņ,Č-ŅCY7C332CYPRESSCPR332ôâ â ô ô –   ôâPà +Ņ,Č-Ņ MAX_FMY_344CYPRESSEPM5032.rô ö r ô  dč # MAX_FMY_343CYPRESSEPM5064.rô â r Š  dč(   # MAX_FMY_342CYPRESSEPM5128.rô â r Š  dč(( (# CYP_7C361_FMYCYPRESSCY7C361ôâ â ô     *3#ô$&%) CYP18G8CYPRESSCYP18G8 ôâ â ô ô –  ô   ôâô*   +Ņ,ú-ŅCY100E301_FAMILYCYPRESSCY_30Xô3 3 ô ô –  ôL      CYP_C22V10DCYPRESSCY22V10D&° ° ô ô –  d    °  +ā,Č-ā CYP_7B337CYPRESSCY7B33Xôļ ļ ô ô –   ôļ+Ö+Ņ,Č-ŅCYP610CYPRESSCY7B326ôļ ļ ô ô  2č Xû   +ô,Č-ôCY7B333B_FAMILYCYPRESSCY7B333Bôļ ļ ô ô  2č Xû +ô,Č-ôCYP_20_4CYPRESSCYP20-5ôļ ļ ô ô  d  ôļô* +Ņ,ú-Ņ CE16V8_FMYCYPCYpCE16Vô e ū ū 2 2 ôe    CYP_7C371_FMYCYPRESSCYP371ô° ° &   ,, " ",  *#ô$X%)%  !#$%&'()*+CYP_PAL22V10_ARRAYAnd-Or       ,   ! # (˙??˙.˙Ā Output Enable ¸    , €€€€€€€€€€€€€€€€€€€€.˙Ā ArchitectureX     €€€€€€€€€€€€€€€€.˙ĀA. Reset/S. Preset lX    , €€€€€€€€€€€€€€+íĀ.˙ĀCYP_PALC22V10D_ARRAYAnd-Or €     ,  ! #(˙??˙ Output Enable€ ¸    , Architecture€X     A. Reset/S. Preset €lX    ,(íĀCYP_20_PIN_INVERT_ARRAYAnd-Or        ! # .˙CYP_PAL20G10_ARRAYAnd-Or Ā     ,   ! # .˙Ā Output EnableĀ ¸    , €€€€€€€€€€€€€€€€€€€€.˙Ā Architecturex     €€€€€€€€€€€€€€€€.˙ĀCYP_PAL20RA10_ARRAYAnd-Or€     (P   !$%"#()&'   ! #  Architecture€      €€€€€€€€€€€€€€€€.˙ĀCYP_PAL22V10C_ARRAYAnd-Or €      @        ,   ! # (˙??˙.˙Ā Output Enable€ ¸     , .˙Ā Architecture€X     ?????????? .˙ĀA. Reset/S. Preset€lX    , CYP_PAL22VP10C_ARRAYAnd-Or €      @        ,   ! # (˙??˙.˙Ā Output Enable€ ¸     , .˙ĀArchitecture (C0 & C1)€X     ?????????? .˙ĀArchitecture (C2)€l     ?????????? .˙ĀA. Reset/S. Preset€vX    , CYP_PAL20R8_ARRAYAnd-Or     , X   !$%"#()&'*+  ! # %đ&đ'đ( ˙˙.˙Ā Output EnableR  ¸    , X   !$%"#()&'*+(˙Ā€€€€€€€€€€€€€€€€€€€€.˙ĀC0B (     (˙Ā€€€€€€€€€€€€€€.˙ĀC1D 2     +˙Ā,˙Ā-€@€€€€€€€€€€€€€€.˙Ā P-TERM OED <     +˙Ā,˙Ā-€€€€€€€€€€€€€€€.˙ĀCYP_PAL20R6_ARRAYAnd-Or°     , X   !$%"#()&'*+  ! # %đ&đ'đ( ˙€€˙.˙Ā Output Enable° P    , X   !$%"#()&'*+%đ&đ'đ(ŋ@€€€€€€€€€€€€€€€€€€€€.˙ĀC0B      (˙Ā€€€€€€€€€€€€€€.˙ĀC1D      +˙Ā,˙Ā-ĀĀ€€€€€€€€€€€€€€.˙Ā P-TERM OED      +˙Ā,˙Ā-?€€€€€€€€€€€€€€.˙ĀCYP_PAL20R4_ARRAYAnd-Or`     , X   !$%"#()&'*+  ! # %đ&đ'đ( ˙€€€€˙.˙Ā Output Enable`      , X   !$%"#()&'*+%đ&đ'đ(ž@€€€€€€€€€€€€€€€€€€€€.˙ĀC0D      +˙Ā,-€€€€€€€€€€€€€€.˙ĀC1D      +˙Ā,˙Ā-áĀ€€€€€€€€€€€€€€.˙Ā P-TERM OED      +˙Ā,˙Ā-€€€€€€€€€€€€€€.˙ĀCYP_PAL20L8_ARRAYAnd-OrĀ     , X   !$%&'()*+"#  ! # %đ&đ'đ( ˙€€€€€€€€˙.˙Ā Output EnableĀ@    , X   !$%&'()*+"#%đ&đ'đ(€@€€€€€€€€€€€€€€€€€€€€.˙ĀC0D      (˙Ā€€€€€€€€€€€€€€.˙ĀC1D      +˙Ā,˙Ā-˙Ā€€€€€€€€€€€€€€.˙Ā P-TERM OEB      (˙Ā€€€€€€€€€€€€€€.˙ĀCYP_PAL20L10_ARRAYAnd-Or°     , X   !$%"#()*+&'  ! # %đ&đ'đ( .˙Ā Output Enable°    , X   !$%"#()*+&'%đ&đ'đ€€€€€€€€€€€€€€€€€€€€.˙ĀC0B @    (˙Ā€€€€€€€€€€€€€€.˙ĀC1D J    +˙Ā,˙Ā-˙Ā€€€€€€€€€€€€€€.˙Ā P-TERM OEB T    (˙Ā€€€€€€€€€€€€€€.˙ĀCYP_PAL20L2_ARRAYAnd-Or€     , X    !"#$%&'()*+  ! # %đ&đ'đ( ˙˙˙˙˙˙˙˙.˙Ā Output EnableT €¸    , X    !"#$%&'()*++˙Ā, - €€€€€€€€€€€€€€€€€€€€.˙ĀC0D 8    (˙Ā€€€€€€€€€€€€€€.˙ĀC1D B    +˙Ā,˙Ā-˙Ā€€€€€€€€€€€€€€.˙Ā P-TERM OEB L    (˙Ā€€€€€€€€€€€€€€.˙ĀCYP_PAL18L4_ARRAYAnd-Or€     , X    !"#$%&'()*+  ! # %3đ&3đ'3đ( ˙˙˙˙˙˙.˙Ā Output EnableT €    , X    !"#$%&'()*++˙Ā,-€€€€€€€€€€€€€€€€€€€€.˙ĀC0B €    (˙Ā€€€€€€€€€€€€€€.˙ĀC1D B    +˙Ā,˙Ā-˙Ā€€€€€€€€€€€€€€.˙Ā P-TERM OEB L    (˙Ā€€€€€€€€€€€€€€.˙ĀCYP_PAL16L6_ARRAYAnd-Or€     , X    !"#$%&'()*+  ! # %30đ&30đ'30đ( ˙˙??˙˙.˙Ā Output EnableT     , X    !"#$%&'()*++˙Ā,?-?€€€€€€€€€€€€€€€€€€€€.˙ĀC0B     (˙Ā€€€€€€€€€€€€€€.˙ĀC1D     +˙Ā,˙Ā-˙Ā€€€€€€€€€€€€€€.˙Ā P-TERM OEB     (˙Ā€€€€€€€€€€€€€€.˙ĀCYP_PAL14L8_ARRAYAnd-Or0     , X    !"#$%&'()*+  ! # %333đ&333đ'333đ( ˙˙˙˙˙˙.˙Ā Output EnableR     , X    !"#$%&'()*+(˙Ā)€*€€€€€€€€€€€€€€€€€€€€€.˙ĀC0B     (˙Ā€€€€€€€€€€€€€€.˙ĀC1D     +˙Ā,˙Ā-˙Ā€€€€€€€€€€€€€€.˙Ā P-TERM OEB     (˙Ā€€€€€€€€€€€€€€.˙ĀCYP_PAL12L10_ARRAYAnd-Orā     , X    !"#$%&'()*+  ! # %3330đ&3330đ'3330đ( ??????????.˙Ā Output EnableBā    ,(˙Ā)˙Ā*˙ĀC0B ā    (˙Ā€€€€€€€€€€€€€€.˙ĀC1D ę    +˙Ā,˙Ā-˙Ā€€€€€€€€€€€€€€.˙Ā P-TERM OEB ô    (˙Ā€€€€€€€€€€€€€€.˙Ā CY7C330_ARRAY PTERM Top€B!    B    !" #B$ PTERM Bottom€B!B!    B #B$Arch C0,C1,C2,C3€„B*   CC#$Arch C4€ŽB    BB#$ CY7C331_ARRAY PTERM Top€@   ` >     !"#$%&'(!"#>$ PTERM Bottom€@@   ` > #>$ Arch C0,C1,C2€€.    BB#$ CY7C335_ARRAY PTERM Top€D"    D   !" #D$ PTERM Bottom€D"D"    D #D$Arch C0-C2,CX (11-16),C3-C5€ˆDR   RCC#$  Arch C6-C10€ÚD     BB#$ CY7C332_ARRAY PTERM Top€Ā   ` 2   !"#2$ PTERM Bottom€ĀĀ   ` 2 #2$Pin 1 & 2 Macro bits€€%     B#Left Arch Bits€†%,    B#Right Arch bits€˛%<      D#Top Miser Bits€î%`   `P#Bottom Miser Bits€N&`   `P# 344_ARRAY Data Array  ˙˙˙˙˙˙ (˙'''''(˙ ­°Ŋ˙ū§­ˇŊ˙ū   !(˙"˙ūException Bit Array  Error_Log Array   343_ARRAY Data Array  ˙˙˙˙˙˙ (˙'''''(˙ ­°Ŋ˙ū§­ˇŊ˙ū &! "#(" $'Exception Bit Array  Error_Log Array   342_ARRAY Data Array  ˙˙˙˙˙˙ (˙'''''(˙ ­°Ŋ˙ū§­ˇŊ˙ū ! "  Exception Bit Array  Error_Log Array   CY7C361_ARRAY INPUT ARRAY „đ   X( ?) ?* 8  !# OUTPUT ARRAY„đĩ   !  Architecture & Config. Bits Data„Ĩ    ( Architecture Bits Data (Contin.)„E    CYP_PAL18G8_ARRAYAnd-Or     $  ! # .˙Ā Output Enable@ ¸     $.˙Ā Architecture@      .˙ĀCYP_20_5_PIN_INVERT_ARRAYAnd-Or €     @€   ! # .˙CYP_20_4_PIN_INVERT_ARRAYAnd-Or €     @€ ! #.˙CY100E301_ARRAYAnd-Or       €€€€€€€€€€€€€€€€   !.˙Output Polarity    P€€€€€€€€€€€€.˙CY100E302_ARRAYAnd-Or       €€€€€€€€€€€€€€€€(˙˙˙˙   !.˙Output Polarity    P€€€€€€€€€€€€+Ã.˙ CY7B337_ARRAYOutput/Product Terms Array       !# CY7B336_ARRAYOutput/Product Terms Array€        !# 610_ARRAYAND     (   ! "#$ P !"#$%&'76543210Macrocell 1-16 I/O Arch P       TURBO bit #1P     TURBO bit #2Q    CY7B333B_ARRAYAND0      2     ! " #$ d !"#$%&'()*+;:9876543210 Global RST1 PT 2    2 d !"#$%&'()*+;:9876543210Global RST2 PTR2    2 d !"#$%&'()*+;:9876543210Macrocell 1-16 I/O Arch„P     Tag BitÔ     CE16V8_ARRAYAnd/Or     ! # local Arch - bits CL1n€  ) UES Array€@   @(local Arch - bits CL0n€H  )product term disable€P@  @* global bits €  ) CY7C371_ARRAYARRAY A€0   VH  ()*+  !# !#$%&'Array A Config. Bits€0Ā    ARRAY B€đ0   VHArray B Config. Bits€ 1Ā    Array A & B Config. Bits€ā1ú   ũUser Id€Ú3