7AMD/MMI PLD Library #4 [Specialty Devices] - V2.20C12013& AmPAL23S8Pal-Based Sequencer AMD_20_23S8AMD_23S8_ARRAY 00C dJ n  BDFHJLNPRTVX d |6t`  d6 ,4BDFHJLNPRTVX dth10035&Am2971Programmable Event Generator AMD_PEG_24AMD_2971_ARRAY 00C 10036& Am29PL141Field-Programmable ControllerAMD_FPC_28_141AMD_29PL141_ARRAY 00C 12258& Am29PL142Field-Programmable Controller AMD_FPC_28AMD_29PL142_ARRAY 00C 12412& Am29CPL141"CMOS Field-Programmable Controller AMD_CPL_28AMD_CPL141_ARRAY 00C 12449& Am29CPL151"CMOS Field-Programmable Controller AMD_CPL_28AMD_CPL141_ARRAY 00C 12414& Am29CPL142"CMOS Field-Programmable Controller AMD_CPL_28AMD_CPL142_ARRAY 00C 12416& Am29CPL152"CMOS Field-Programmable Controller AMD_CPL_28AMD_CPL142_ARRAY 00C 12417& Am29CPL154"CMOS Field-Programmable Controller AMD_CPL_28AMD_CPL144_ARRAY 00C 12307&PLS105"Field-Programmable Logic Sequencer 28_PIN_FPLS`IFL_PLS105_ARRAY 00C      12308& PLS167A/B"Field-Programmable Logic Sequencer 24_PIN_FPLS`IFL_PLS167_ARRAY 00C 9  9 12309& PLS168A/B"Field-Programmable Logic Sequencer PLS168_FMY`IFL_PLS168_ARRAY 00C      12548&PLS30S16"Field-Programmable Logic Sequencer 28_PINS_FPLS@IFL_PLS30_ARRAY 00C 10618&PMS14R2114H2 PAL & 128*8 PROM MMI_PROSE@MMI_PROSE_ARRAY 01C 10616& PAL10H20P8-Gate Array w/ Prod.Term Sharing. Bypass Fuses MMI_10HPAL@MMI_20P8_ARRAY 00C 10617& PAL10H20G8-Gate Array w/ Prod.Term Sharing. Bypass Fuses MMI_10HPAL@MMI_20G8_ARRAY 00C 11979&PAL10H/10020EV8,And-Or Array w/ Polarity & Reg. Bypass FusesAMD_ECL@ 20EV8_ARRAY 00C 11980&PAL10H/10020EG8-And-Or Array w/ Polarity & Latch Bypass FusesAMD_ECL@ 20EV8_ARRAY 00C  AMD_20_23S8AMDAMD23S8L  0   2      AMD_PEG_24AMDAMD2971   2     AMD_FPC_28AMDAMD_FPC  D   2  AMD_FPC_28_141AMDAMD_FPC1  D   2   AMD_CPL_28AMDAMD_CPL F :     #l 28_PIN_FPLSMMIMMI_PLS  D   *3 24_PIN_FPLSMMIMMI_PLS  D  P  *3 PLS168_FMYMMIPLS168  D  P  *3 28_PINS_FPLSAMDAMD_PLSL  &   2 XL  MMI_PROSEMMIMMI_PROS   & 2        MMI_10HPALMMIMMI_HP      AMD_ECLAMD/MMIAMD_ECL(      ( $xAMD_23S8_ARRAYAnd/Output Enable PTs      .\        !# (.And (Buried Registers)   .\      ( ?0+.Observability PT .   .\      +. Synch. Preset/Asynch. Reset PT's @\  .\      +.S0/S1@B   .S2/S3 @R  (<.AMD_2971_ARRAYNext Addr/Event Gen Fuses@    ! #Start Address Generator Fuses@(    Timing and Control Fuses0h   AMD_29PL141_ARRAY Data (Jedec)  @   @ !# AMD_29PL142_ARRAY Data (Jedec)@   " D !# SSR Fuse@    EXP Fuse@    AMD_CPL141_ARRAY Data (Jedec)  @ @ !# Test Inputs Config. Bits0  EXP / SSR / RESET Config. Bits0  AMD_CPL142_ARRAY Data (Jedec)  "D !# Test Inputs Config. Bits0  EXP / SSR / RESET Config. Bits0  AMD_CPL144_ARRAY Rows 0-255$  $H !#  Rows 256-511$$  $HTest Inputs Config. Bits0H   EXP / SSR / RESET Config. Bits0H   IFL_PLS105_ARRAY And Array/Or Array (Logic Terms)  0J@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijkl ! $  PR/OE Option0   3 Test Columnsp (  0123J@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijkl IFL_PLS167_ARRAY And Array/Or Array (Logic Terms)  0F@ABCDEFGHIJKNOPQRSTUVWXYZ[\]LM^_jkhifgdebc`al   !$  PR/OE Option0   3 Test Columnsp!   0123F@ABCDEFGHIJKNOPQRSTUVWXYZ[\]LM^_jkhifgdebc`al   IFL_PLS168_ARRAY And Array/Or Array (Logic Terms)  0J@ABCDEFGHIJKPQRSTUVWXYZ[NO\]LM^_`abcdefghijkl !$  PR/OE Option0   3 Test Columnsp (  0123J@ABCDEFGHIJKPQRSTUVWXYZ[NO\]LM^_`abcdefghijkl IFL_PLS30_ARRAY And Array/Or Array (Logic Terms)  @j  +*-,/.10#"%$'&)(32547698! :;A@BLMNIJKFGHCDEOVWSTUPQR! # Output Enable0   (0<x  +*-,/.10#"%$'&)(32547698! :;Architecture Fuses$   @  MMI_PROSE_ARRAY PROM         !#And/Or           Architecture@       MMI_20P8_ARRAYAnd0    @5.6/+3 ,4 <$;#'>&=(  P%=#;'?+3 -5/7 )1.6 &>!9 !#Output Polarity0    *"2:  P.T. Share - Pins 4,5,7,80    5.6/+3 ,4   "*P.T. Share - Pins 17,18,20,210(    <$;#'>&=  2:MMI_20G8_ARRAYAnd0    @5.6/+3 ,4 <$;#'>&=(  P%=#;'?+3 -5/7 )1.6 &>!9 !# Latch Bypass0    *"2:  P.T. Share - Pins 4,5,7,80    5.6/+3 ,4   "*P.T. Share - Pins 17,18,20,210(    <$;#'>&=  2: 20EV8_ARRAYAnd0  Z  om|kzixgvIGVETCRAPecrap/>-<+:)8'%4#2!0O^M\KZusbq`?.=,;*9(75$3"1 _N]L[J}l{jyhwfYWFUDSBQ@( P:89/.&'071;<=>?56432 !#Architecture 1-40      ,Architecture 5-80     %-