E$ˇ,ū7AMD/MMI PLD Library #3 [24 pin Std. Devices] - V2.20C12411&PAL22IP6"Registered Async And-Or Gate Array 22IP6_FMY 22IP6_ARRAY 00x 10018& AmPAL22V10(And-Or Gate Array with Output Macrocells AMD_PAL_24°AMD_22V10_ARRAY 00C `,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙12726&PAL22V10(And-Or Gate Array with Output Macrocells AMD_PAL_24°AMD_22V10_ARRAY 00C `,X¸äœČØl˜X „ DpØ@ø$„°Ä `lt¨˙˙˙|˙˙˙\P˙˙˙L$˙˙˙ä øū˙˙$ Ėū˙˙d ū˙˙ütū˙˙ėHū˙˙4ū˙˙¨˙˙˙ ``(P  xˆ@ Ėø$P|¨Ô,Xl˜Ä `X„°Ü4`Œ¸äŒë˙˙ėė˙˙¤î˙˙´đ˙˙ķ˙˙Üõ˙˙œø˙˙û˙˙ũ˙˙Ėū˙˙X”é˙˙ė˙˙˙12862& PAL20L8-7And-Or-Invert Gate Array AMD_20XX-7AMD_20XX-7_INVERT_ARRAY 00C 14105& PAL20L8-5And-Or-Invert Gate Array AMD_20XX-7AMD_20XX-7_INVERT_ARRAY 00C 12483& PAL20R8-7Registered And-Or Gate Array AMD_20XX-7AMD_20XX-7_INVERT_ARRAY 00C 14108& PAL20R8-5Registered And-Or Gate Array AMD_20XX-5AMD_20XX-7_INVERT_ARRAY 00B 12864& PAL20R6-7Registered And-Or Gate Array AMD_20XX-7AMD_20XX-7_INVERT_ARRAY 00C 14107& PAL20R6-5Registered And-Or Gate Array AMD_20XX-5AMD_20XX-7_INVERT_ARRAY 00C 12863& PAL20R4-7Registered And-Or Gate Array AMD_20XX-7AMD_20XX-7_INVERT_ARRAY 00C 14106& PAL20R4-5Registered And-Or Gate Array AMD_20XX-5AMD_20XX-7_INVERT_ARRAY 00C 10020& AmPAL20L8And-Or-Invert Gate ArrayAMD_PAL_24_STDAMD_20L8_ARRAY 00C 10023& AmPAL20R8Registered And-Or Gate ArrayAMD_PAL_24_STDAMD_20L8_ARRAY 00C 10022& AmPAL20R6Registered And-Or Gate ArrayAMD_PAL_24_STDAMD_20L8_ARRAY 00C 10021& AmPAL20R4Registered And-Or Gate ArrayAMD_PAL_24_STDAMD_20L8_ARRAY 00C 10024& AmPAL20L10#Registered And-Or-Invert Gate ArrayAMD_PAL_24_STDAMD_20L10_ARRAY 00C 10025& AmPAL22P10,And-Or Gate Array with Prog. Output PolarityAMD_PAL_24_STDAMD_22P10_ARRAY 00C 10026& AmPAL20RP4,Reg. And-Or Array with Prog. Output PolarityAMD_PAL_24_STDAMD_20RP4_ARRAY 00C 10027& AmPAL20RP6,Reg. And-Or Array with Prog. Output PolarityAMD_PAL_24_STDAMD_20RP6_ARRAY 00C 10028& AmPAL20RP8,Reg. And-Or Array with Prog. Output PolarityAMD_PAL_24_STDAMD_20RP8_ARRAY 00C 10029& AmPAL20RP10,Reg. And-Or Array with Prog. Output PolarityAMD_PAL_24_STDAMD_20RP10_ARRAY 00C 10030& AmPAL22XP10+And-Or-Xor Array with Prog. Output PolarityAMD_PAL_24_STDAMD_22P10_ARRAY 00C 10031& AmPAL20XRP4,Reg. And-Or-Xor Array with Prog. Output Pol.AMD_PAL_24_STDAMD_20RP4_ARRAY 00C 10032& AmPAL20XRP6,Reg. And-Or-Xor Array with Prog. Output Pol.AMD_PAL_24_STDAMD_20RP6_ARRAY 00C 10033& AmPAL20XRP8,Reg. And-Or-Xor Array with Prog. Output Pol.AMD_PAL_24_STDAMD_20RP8_ARRAY 00C 10034& AmPAL20XRP10,Reg. And-Or-Xor Array with Prog. Output Pol.AMD_PAL_24_STDAMD_20RP10_ARRAY 00C 10576&PAL12L10And-Or-Invert Gate ArrayMMI_24@PAL12L10_ARRAY 00C 10577&PAL14L8And-Or-Invert Gate ArrayMMI_24@ PAL14L8_ARRAY 00C 10578&PAL16L6And-Or-Invert Gate ArrayMMI_24@ PAL16L6_ARRAY 00C 10579&PAL18L4And-Or-Invert Gate ArrayMMI_24@ PAL18L4_ARRAY 00C 10580&PAL20L2And-Or-Invert Gate ArrayMMI_24@ PAL20L2_ARRAY 00C 10581&PAL20C1And-Or/And-Or-Invert Gate ArrayMMI_24@ PAL20C1_ARRAY 00C 10582&PAL20L10And-Or-Invert Gate ArrayMMI_24@PAL20L10_ARRAY 00C 10583& PAL20L10AAnd-Or-Invert Gate ArrayMMI_24@PAL20L10_ARRAY 00C 10584&PAL20X10 Registered And-Or-Xor Gate ArrayMMI_24_XPPAL20X10_ARRAY 00C 10585& PAL20X10A Registered And-Or-Xor Gate ArrayMMI_24_XĐPAL20X10_ARRAY 00C 10586&PAL20X8 Registered And-Or-Xor Gate ArrayMMI_24_XP PAL20X8_ARRAY 00C 10587&PAL20X8A Registered And-Or-Xor Gate ArrayMMI_24_XĐ PAL20X8_ARRAY 00C 10588&PAL20X4 Registered And-Or-Xor Gate ArrayMMI_24_XP PAL20X4_ARRAY 00C 10589&PAL20X4A Registered And-Or-Xor Gate ArrayMMI_24_XĐ PAL20X4_ARRAY 00C 10590& PAL20L8A/A-2And-Or-Invert Gate ArrayMMI_24@ PAL20L8_ARRAY 00C 10592&PAL20L8BAnd-Or-Invert Gate ArrayMMI_24@ PAL20L8_ARRAY 00C 20592& PAL20L8B-2And-Or-Invert Gate ArrayMMI_24@ PAL20L8_ARRAY 00C 13744& PAL20L8-10And-Or-Invert Gate ArrayMMI_24@ PAL20L8_ARRAY 00C 12473& PAL24L10-10And-Or-Invert Gate Array MMI_28_-10@PAL24L10_ARRAY 00C 10593& PAL20R8A/A-2Registered And-Or Gate ArrayMMI_24P PAL20R8_ARRAY 00C 10595& PAL20R8B/B-2Registered And-Or Gate ArrayMMI_24P PAL20R8_ARRAY 00C 13745& PAL20R8-10Registered And-Or Gate ArrayMMI_24P PAL20R8_ARRAY 00C 12476& PAL24R10-10Registered And-Or Gate Array MMI_28_-10PPAL24R10_ARRAY 00C 10596& PAL20R6A/A-2Registered And-Or Gate ArrayMMI_24P PAL20R6_ARRAY 00C 10598& PAL20R6B/B-2Registered And-Or Gate ArrayMMI_24P PAL20R6_ARRAY 00C 13746& PAL20R6-10Registered And-Or Gate ArrayMMI_24P PAL20R6_ARRAY 00C 12871& PAL24R8-10Registered And-Or Gate Array MMI_28_-10P PAL24R8_ARRAY 00C 10599& PAL20R4A/A-2Registered And-Or Gate ArrayMMI_24P PAL20R4_ARRAY 00C 10601& PAL20R4B/B-2Registered And-Or Gate ArrayMMI_24P PAL20R4_ARRAY 00C 13747& PAL20R4-10Registered And-Or Gate ArrayMMI_24P PAL20R4_ARRAY 00C 12872& PAL24R4-10Registered And-Or Gate Array MMI_28_-10P PAL24R4_ARRAY 00C 10602&PAL6L16And-Or-Invert Gate ArrayMPL_24 PAL6L16_ARRAY 00C 10603&PAL8L14And-Or-Invert Gate ArrayMPL_24 PAL8L14_ARRAY 00C 10609& PAL20RA10Registered Async And-Or ArrayMAP_24ЀPAL20RA10_ARRAY 00C PAL20RA10-20 Only10610&PAL22RX8"And-Or Gate Array with Flush FusesMRX_24ĐMMI_PAL22RX8_ARRAY 00C 10611& PAL32VX10)And-Or Array with Programmable MacrocellsMVX_24đMMI_PAL32VX10_ARRAY 00C °@€Ā@€Ā@€Ā @ € Ā @€Ā@€ĀĀ@€@€ĀĀ @ € #@#€#Ā#Ā%& & °€%Ā @"˙˙˙@€Ā@ū˙˙@€Ā€ũ˙˙Ā@Āü˙˙Ā@ü˙˙@ €Ā@û˙˙Ā @ €ú˙˙Ā@Āų˙˙@€Āų˙˙@ũ˙˙€˙˙˙Ā@ø˙˙ °€€ €€@€Ā@€Ā @ € Ā !@!€!Ā!"@"€"Ā"#@#€#Ā#$@$€$Ā$%@%€%Ā%& & °Ā€@Ā€@Ā@â˙˙Āä˙˙Āį˙˙@ë˙˙@ī˙˙Āķ˙˙@ø˙˙@ü˙˙Ā˙˙˙Āā˙˙€â˙˙€å˙˙é˙˙í˙˙€ņ˙˙ö˙˙ú˙˙€ũ˙˙€ĀŨ˙˙@ā˙˙@ã˙˙Āæ˙˙Āę˙˙@ī˙˙Āķ˙˙Ā÷˙˙@û˙˙@ū˙˙€Ú˙˙10612&PAL20S10+And-Or Gate Array with Product Term SharingMRS_24@PAL20S10_ARRAY 00C 10613& PAL20RS10+Reg. And-Or Array with Product Term SharingMRS_24ĐPAL20RS10_ARRAY 00C 10614&PAL20RS8+Reg. And-Or Array with Product Term SharingMRS_24ĐPAL20RS10_ARRAY 00C 10615&PAL20RS4+Reg. And-Or Array with Product Term SharingMRS_24ĐPAL20RS4_ARRAY 00C AMD_PAL_24_STDAMDAMD_PL24 Ü 0 Ė – 2  Ü  AMD_PAL_24AMDAMD22V10āā Ü 0 Ö – 2  Ü    MMI_28_-10MMIMMIôŪ Ū & & –   č@( MMI_24MMIMMIô— — &  –     č@(  MMI_24_XMMIMMIô— — &  –     č@(  MPL_24MMIMMI_PL16ô— — &  –  MAP_24MMIMMI_APô— Đ & č –     č@(  MRS_24MMIMMI_RSô— Đ & č –     č@(  MVX_24MMIMMI_VXô— — & –  — MRX_24MMIMMI_RXū° ° 0 –  Đ   22IP6_FMYAMDAM22IP6. . 0 Ė –   . AMD_20XX-7AMDAMDPAL-5ôô Ü  ¸ – 2  Ü2    AMD_20XX-5AMDAM20R8-5ôô Ü   – 2  Ü2   AMD_20L8_ARRAYAnd-Or  L   +    !# %˙&˙'˙+€@.˙ĀAMD_20L10_ARRAYAnd-Or @L   (    !# ( .˙ĀAMD_22P10_ARRAYAnd-OrxL    ,    !# .˙ĀOutput Polarity Fusesx   €€€€€€€€€€€€€€.˙ĀAMD_20RP4_ARRAYAnd-Or p L    (    !# ( .˙ĀOutput Polarity Fusesp    €€€€€€€€€€€€€€.˙ĀAMD_20RP6_ARRAYAnd-Or  L    (    !# ( .˙ĀOutput Polarity Fuses    €€€€€€€€€€€€€€.˙ĀAMD_20RP8_ARRAYAnd-Or Đ L    (    !# ( @ €.˙ĀOutput Polarity FusesĐ    €€€€€€€€€€€€€€.˙ĀAMD_20RP10_ARRAYAnd-Or€ L   (    !# .˙ĀOutput Polarity Fuses€    €€€€€€€€€€€€€€.˙ĀAMD_22V10_ARRAYAnd-Or  L   ,    !"# $(˙??˙.˙Ā Output Enable ¸   ,  €€€€€€€€€€€€€€€€€€€€.˙Ā Arch Fuses == Out Pol - Reg/CombX   €€€€€€€€€€€€€€.˙ĀAsync Reset/Sync Preset lX   ,  €€€€€€€€€€€€€€€€€€€€+íĀ.˙ĀPAL12L10_ARRAYAnd-Orā    PP(  d          !"#$%3330( ??????????.˙Ā PAL14L8_ARRAYAnd-Or0    PP(  d          !"#$%333( ˙??????˙+€@.˙Ā PAL16L6_ARRAYAnd-Or€    PP(  d          !"#$%30( ˙˙??˙˙+ĀĀ.˙Ā PAL18L4_ARRAYAnd-OrĐ    PP(  d          !"#$%3( ˙˙˙˙˙˙+áĀ.˙Ā PAL20L2_ARRAYAnd-Or€    PP(  d          !"#$( ˙˙˙˙˙˙˙˙+ķĀ.˙Ā PAL20C1_ARRAYAnd-Or€    PP(  d          !"#$( ˙˙˙˙˙˙˙˙+ķĀ.ĀPAL20L10_ARRAYAnd-Or @    PP(  d          !"#$( .˙ĀPAL20X10_ARRAYAnd-Or @    PP(  d          !"#$( .˙Ā PAL20X8_ARRAYAnd-Or @    PP(  d          !"#$( .˙Ā PAL20X4_ARRAYAnd-Or @    PP(  d          !"#$( .˙Ā PAL20L8_ARRAYAnd-Or     PP(  d          !"#$+€@.˙ĀPAL24L10_ARRAYAnd-Or ˙    PP0 d      !"#$+€@.˙Ā PAL20R8_ARRAYAnd-Or     PP(  d          !"#$+€@.˙ĀPAL24R10_ARRAYAnd-Or ˙    PP0 d      !"#$+€@.˙Ā PAL20R6_ARRAYAnd-Or     PP(  d          !"#$+€@.˙Ā PAL24R8_ARRAYAnd-Or ˙    PP0 d      !"#$+€@.˙Ā PAL20R4_ARRAYAnd-Or     PP(  d          !"#$+€@.˙Ā PAL24R4_ARRAYAnd-Or ˙    PP0 d      !"#$+€@.˙Ā PAL8L14_ARRAYInvertÄā    P  d  ! #.˙ü PAL6L16_ARRAYInvertÄĀ    P   d  !  #.˙˙PAL20RA10_ARRAYAnd-Or…€    PP(  d           !"#$Polarity Fusesd€    PAL20RS10_ARRAYAnd-Or…€    PP(  d          ! " #$Polarity Fusesd€     Shared Fuses ĨŠ €    PP  €FF€€€€€€€€€€€€€€FF€€€€€€€€€€€€€( ˙˙PAL20S10_ARRAYAnd-Or…€    PP(  d          ! " #$Polarity Fusesd€     Shared Fuses ĨŠ p    PP  €FF€€€€€€€€€€€€€€FF€€€€€€€€€€€€€( ˙€€€€˙PAL20RS4_ARRAYAnd-Or…€    PP(  d          ! " #$Polarity Fusesd€     Shared Fuses ĨŠ x    PP  €FF€€€€€€€€€€€€€€FF€€€€€€€€€€€€€( ˙€€˙MMI_PAL32VX10_ARRAYAnd-Or     PP@    !"#$(˙??˙.˙ĀOutput Enable Product Term A€    PP@  .˙ĀFlush Product Term A€ €    PP@  .˙ĀPolarity Product Term A#€    PP@  .˙ĀSynch Reset/Asynch Preset Á€%€    PP@  +€.˙ĀRegister Polaritya&    PP  .˙ĀMMI_PAL22RX8_ARRAYAnd    P P,  d         !"#$( 0000.˙ Flush Fuses`   P  .˙ 22IP6_ARRAYAnd-Or`   ,     !#$PTS1 Sharing Fuses` 6   PTS2 Sharing Fuses– 6   Polarity FusesĖ   FlushØ   AMD_20XX-7_INVERT_ARRAYAnd-Or L  (    !#.˙