SID in an FPGA with hardware filter, oh my

Well I decided to try to make a SID in the FPGA. So far, I have it playing a SID tune somewhat. This is about 1 day of work so far.

listen to it!

So far, the SID enveloper, waveform generator (with “invalid” bit combinations), and some other goodies are done. For starters, I am outputting the straight and filtered audio separately, so that it can run to my filter circuit.

Unlike all the other FPGA SID implementations out there, mine’s gonna use a real live filter! I have designed and made the filter, and it seems to mostly work. It’s made similar to the filter on the real chip, using MOS transistors and such, so it should accurately model it. I hope. I passed some waveforms through it while I dinked around with the cutoff freq and all that jazz and it sounded pretty decent. We’ll know when I hook it up to the FPGA if I got it or not.

All in all not a bad deal for about 1 day of work. Hopefully tonight I will have a proper “SID core” set up and running. We’ll see.