FPGA Synthesizer Progress

Well it’s been awhile.  I haven’t been lazy, far from it.  Been so busy I haven’t had much chance to update the blog!  I spent the last 2 months learning verilog, and then performing a 100% conversion of my project from schematic entry to 100% verilog!  I didn’t know anything about verilog until having a little discussion with someone about it, and it seemed like a good time to learn it.   I already had a working project in schematic entry (around 150 schematics all linked together in this case) and figured it’d be a good learning experience to port it to verilog.

Long story short, the conversion was a success, and I ended up fixing a few bugs and adding some features along the way.  I ended up 100% redoing my OPL3 core, and vastly simplified and improved it, reducing device resource usage immensely.    To date, I have full support for the following sound chips:  SID (quad),  POKEY (quad), OPL3 (full support),  NES audio, N106 (8 chan wavetable), VRC6 (3 channels), VRC7 (FM synth), MMC5 (two squares+digi), FME7 (3 squares), and FDS audio (1 chan wavetable).  The wishlist of additions is:   Atari 2600 with extended range, Gameboy sound, and coleco/SMS sound (SN76489).  These shouldn’t be too tough, but before I can implement those I need to emulate the target CPUs which are Z80 and GBCPU.

This leads me to the current work:  I created a small RISC CPU for the FPGA which can emulate other 8 bit CPUs with cycle accuracy.  I figured that emulating the 8 bit CPUs would be by far more resource efficient on the FPGA, since to change the emulated CPU I only have to change the code in the block RAM.  Thus, 6502, Z80, GB CPU, etc. can be accomodated without sacrificing accuracy or speed, while only requiring one peice of hardware.  Ironically, the RISC CPU is smaller than the 6502 it will replace in FPGA resources.  The only minor downside is the 4K of blockRAM I used, but that’s a small price to pay ultimately for what it can do.

The specs on the CPU are:  18 bit instruction word, single cycle instructions, 32 bytes of RAM,  single and dual byte address modes, and a few special instructions to make CPU emulation easier such as jump tables and bit setting and clearing.  I named it the “KevRISC”  CPU 🙂